1. Field of the Invention
The present invention relates to a forced error generating circuit for a data processing unit comprising a number of structural elements. More particularly, it relates to such circuit for inspecting whether or not the function for error detection of the data processing unit is correctly operated, by forcibly causing error in each of the structural elements.
2. Background Information
FIG. 3 is a block diagram of a conventional forced error generating circuit for a data processing unit. In FIG. 3, a reference numeral 1 designates a forced error register in which data "0" to "3" are input, a numeral 2 designates a counter in which data "4" to "7" are input, a numaral 3 designates an error generating circuit, a numeral 4 designates an error detecting circuit, a numeral 5 designates an AND gate, a numeral 6 designates a NAND gate, a numeral 7 designates a count-down starting signal for starting count down, a numeral 8 designates a forced error designation signal outputted from the forced error register 1, a numeral 9 designates a forced error controlling signal outputted from the counter 2, a numeral 10 designates a forced error generating signal outputted from the AND gate 5, a numeral 11 designates a parity which is inputted into the error generating circuit 3 to be used for data "8" to "11", a numeral 12 designates a parity as an output from the error generating circuit 3 which is inputted into the error detecting circuit 4 to be used for data "8" to "11", and the numeral 13 designates an error detecting signal outputted from the error detecting circuit 4.
The operation of the conventional forced error generating circuit will be described. By the execution of a forced error generating instruction for diagnosis, data "0" to "3" each of which specifies each structural element from which error is forcibly produced, are inputted into the forced error register 1 and are set therein, whereby the forced error designation signal 8 corrsponding to any one of the structural elements in which the error is forcibly produced, becomes significant. Then, values specified by the data "4" to "7" are set in the counter 2, and the count-down starting signal 7 is made significant. Then, the data "4" to "7" as the content of the counter 2 are sequentially counted down for each machine cycle. When outputs "0" to "3" to be produced from the counter 2 do not appear at all, the forced error controlling signal 9 is provided from the NAND gate 6.
Subsequent to the forced error designation signal 8 made previously significant, when the forced error controlling signal 9 becomes significant, the forced error generating signal 10 is provided from the AND gate 5. Under the normal condition that the forced error generating signal 10 is not significant, the error generating circuit 3 outputs the parity 11 for data "8" to "11" as the parity 12. The error detecting circuit 4 receives the data "8" to "11" and the parity 12 to conduct a parity check. When a parity error is found in the parity check, the error detecting signal 13 is made significant.
On the other hand, when the forced error generating signal 10 is made "signficant" by the execution of the forced error generating instruction for diagnosis, the error generating circuit 3 reverses the inputted parity 11 to output it as the parity 12. Thus, since the parity for the data "8" to "11" to be inputted into the error detecting circuit 4 is reversed, the parity check makes the error detecting signal 13 significant. Thus, the correct functioning of the detecting circuit 4 is confirmed.
While the conventional forced error generating circuit having the construction as above-mentioned has an advantage that timing of forcibly causing of the error can be finely adjusted by suitably selecting a proper sitting for the initial constant for the counter, it has the drawbacks that it is impossible to forcibly produce the error in order to conduct inspection unless an operator is not well acquainted with the function of the instructions and hardware used and it is necessary to use a number of the hardware such as the counter.